Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur

Version 1.0 Date: 2015-01-20 Hardware Data Sheet Section III ET1815 / ET1816 Slave Controller IP Core for Xilinx® FPGAs Release 2.04e Sectio

FIGURES III-X Slave Controller – IP Core for Xilinx FPGAs FIGURES Figure 1: EtherCAT IP Core Block Diagram ...

PDI Description III-88 Slave Controller – IP Core for Xilinx FPGAs C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sa

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-89 C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late

PDI Description III-90 Slave Controller – IP Core for Xilinx FPGAs SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sampl

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-91 SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sam

PDI Description III-92 Slave Controller – IP Core for Xilinx FPGAs 10.3 Asynchronous 8/16 bit µController Interface 10.3.1 Interface The asynchrono

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-93 10.3.3 µController access The 8 bit µController interface reads or writes 8 bit

PDI Description III-94 Slave Controller – IP Core for Xilinx FPGAs 10.3.6 µController access errors These reasons for µController access errors are

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-95 10.3.8 Connection with 8 bit µControllers If the ESC is connected to 8 bit µCon

PDI Description III-96 Slave Controller – IP Core for Xilinx FPGAs 10.3.9 Timing Specification Table 53: µController timing characteristics IP Core

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-97 Parameter Min Max Comment tADR_BHE_DATA_hold x10 ADR, BHE and Write DATA valid

FIGURES Slave Controller – IP Core for Xilinx FPGAs III-XI Figure 61: SyncSignal timing ...

PDI Description III-98 Slave Controller – IP Core for Xilinx FPGAs tCS_RD_to_DATA_releaseBHEtADR_BHE_setupCSBHERDWRDATABUSYDATAADRADRtCS_to_BUSYtread

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-99 BHE1CSBHEWRRDDATABUSYADR1ADRtWR_activetWR_to_BUSYtCS_delaytWR_delaytADR_BHE_DATA

PDI Description III-100 Slave Controller – IP Core for Xilinx FPGAs 10.4 PLB Slave Interface 10.4.1 Interface The PLB v4.6 slave PDI is selected du

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-101 Signal Direction Description Signal polarity PLB_IRQ_MAIN OUT Interrupt act. hi

PDI Description III-102 Slave Controller – IP Core for Xilinx FPGAs 10.4.3 Timing specifications Table 56: PLB timing characteristics Parameter Min

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-103 PLB_SPLB_CLKPLB_ABusADRPLB_RNWPLB_Sl_RdDackPLB_Sl_RdCompPLB_Sl_rdDBusDATAtReadP

PDI Description III-104 Slave Controller – IP Core for Xilinx FPGAs 10.5 OPB Slave Interface 10.5.1 Interface The OPB Slave PDI is selected during

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-105 10.5.2 Configuration The OPB interface has PDI type 0x80 in the PDI control re

PDI Description III-106 Slave Controller – IP Core for Xilinx FPGAs 10.5.4 Timing specifications Table 58: OPB timing characteristics Parameter Min

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-107 CLKOPBABUSADRRNWSL_XFERACKSL_DBUSDATAtReadCStClkSL_TOUTSUPBEBE Figure 57: OPB R

ABBREVIATIONS III-XII Slave Controller – IP Core for Xilinx FPGAs ABBREVIATIONS µC Microcontroller ADR Address AL Application Layer BHE Bus High En

Distributed Clocks SYNC/LATCH Signals III-108 Slave Controller – IP Core for Xilinx FPGAs 11 Distributed Clocks SYNC/LATCH Signals For details about

SII EEPROM Interface (I²C) Slave Controller – IP Core for Xilinx FPGAs III-109 12 SII EEPROM Interface (I²C) For details about the ESC SII EEPROM

Electrical Specifications III-110 Slave Controller – IP Core for Xilinx FPGAs 13 Electrical Specifications Table 63: AC Characteristics Symbol Param

Synthesis Constraints Slave Controller – IP Core for Xilinx FPGAs III-111 14 Synthesis Constraints The following table contains basic IP Core cons

Synthesis Constraints III-112 Slave Controller – IP Core for Xilinx FPGAs Example User Constraints File (UCF) ######################## ### Global CLK

Synthesis Constraints Slave Controller – IP Core for Xilinx FPGAs III-113 ################## ### MII Port 2 ### ################## ### Receive clo

Appendix III-114 Slave Controller – IP Core for Xilinx FPGAs 15 Appendix 15.1 Support and Service Beckhoff and their partners around the world offe

Overview Slave Controller – IP Core for Xilinx FPGAs III-1 1 Overview The EtherCAT IP Core is a configurable EtherCAT Slave Controller (ESC). It t

Overview III-2 Slave Controller – IP Core for Xilinx FPGAs 1.1 Frame processing order The frame processing order of the EtherCAT IP Core is as follo

Overview Slave Controller – IP Core for Xilinx FPGAs III-3 1.2 Scope of this document Purpose of this document is to describe the installation and

Overview III-4 Slave Controller – IP Core for Xilinx FPGAs 1.4 Target FPGAs The EtherCAT IP Core for Xilinx® FPGAs is targeted at these FPGA familie

Overview Slave Controller – IP Core for Xilinx FPGAs III-5 1.6 Tested FPGA/Designflow combinations The EtherCAT IP Core has been synthesized succe

Overview III-6 Slave Controller – IP Core for Xilinx FPGAs 1.7 Release Notes EtherCAT IP Core updates deliver feature enhancements and removed restr

Overview Slave Controller – IP Core for Xilinx FPGAs III-7 The IP Core version, denoted as X.Yz (e.g., 1.00a), consists of three values X, Y, and z

DOCUMENT ORGANIZATION III-II Slave Controller – IP Core for Xilinx FPGAs DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) docum

Overview III-8 Slave Controller – IP Core for Xilinx FPGAs 1.8 Design flow The design flow for creating an EtherCAT Slave Controller based on the Et

Overview Slave Controller – IP Core for Xilinx FPGAs III-9 1.9 IP Core Evaluation The EtherCAT IP Core for Xilinx FPGAs supports IP core evaluatio

Overview III-10 Slave Controller – IP Core for Xilinx FPGAs 1.10 Simulation A behavioral simulation model of the EtherCAT IP core is not available b

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-11 2 Features and Registers 2.1 Features Table 7: IP Core Feature Details

Features and Registers III-12 Slave Controller – IP Core for Xilinx FPGAs Feature IP Core Xilinx® V2.04e IP Core Xilinx V2.04d Output high-Z if WD

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-13 Feature IP Core Xilinx® V2.04e IP Core Xilinx V2.04d Lost Link Counter

Features and Registers III-14 Slave Controller – IP Core for Xilinx FPGAs Feature IP Core Xilinx® V2.04e IP Core Xilinx V2.04d Example designs/ pre-s

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-15 2.2 Registers An EtherCAT Slave Controller (ESC) has an address space of

Features and Registers III-16 Slave Controller – IP Core for Xilinx FPGAs Address Length (Byte) Description IP Core V2.4.0-V2.4.4/ V2.04a-V2.04e Reg

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-17 Address Length (Byte) Description IP Core V2.4.0-V2.4.4/ V2.04a-V2.04e R

DOCUMENT HISTORY Slave Controller – IP Core for Xilinx FPGAs III-III DOCUMENT HISTORY Version Comment 1.0  Initial release EtherCAT IP Core for

Features and Registers III-18 Slave Controller – IP Core for Xilinx FPGAs Table 10: Legend Symbol Description x Available - Not available r Read only

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-19 2.3 Extended ESC Features in User RAM Table 11: Extended ESC Features (R

Features and Registers III-20 Slave Controller – IP Core for Xilinx FPGAs Bit Description small medium large 44 Reserved 0 0 0 45 Reserved 0 0 0 46 R

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-21 3 IP Core Installation 3.1 Installation on Windows PCs 3.1.1 System Requ

IP Core Installation III-22 Slave Controller – IP Core for Xilinx FPGAs 3.2 Installation on Linux PCs 3.2.1 System Requirements The system requirem

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-23 3.4 License File The license file for the EtherCAT IP Core (iptb_ethercat_

IP Core Installation III-24 Slave Controller – IP Core for Xilinx FPGAs 3.6 RSA Decryption Keys The Xilinx XST synthesis flow requires two decryptio

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-25 3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow 3.9 Softw

IP Core Usage III-26 Slave Controller – IP Core for Xilinx FPGAs 4 IP Core Usage 4.1 IPCore_Config Tool This chapter explains how to configure your

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-27 - A VHDL package which contains the component declaration of the IP Core (pk_<

CONTENTS III-IV Slave Controller – IP Core for Xilinx FPGAs CONTENTS 1 Overview 1 1.1 Frame processing order 2 1.2 Scope of this document 3 1.

IP Core Usage III-28 Slave Controller – IP Core for Xilinx FPGAs 8. Now you can find your user configured EtherCAT IP Core in the IP Catalog for add

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-29 Figure 9: EDK – Configuration Dialog 10. Assign addresses to the EtherCAT IP Core

IP Core Usage III-30 Slave Controller – IP Core for Xilinx FPGAs 11. The tab "Ports" in the "System Assembly View" shows the conn

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-31 12. Generate Bitstream: Result is the file "system.bit" in the implement

IP Core Configuration III-32 Slave Controller – IP Core for Xilinx FPGAs 5 IP Core Configuration Figure 12: EtherCAT IP Core Configuration Interfac

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-33 5.1.1 Product ID tab Figure 13: Product ID tab PRODUCT_ID input in decim

IP Core Configuration III-34 Slave Controller – IP Core for Xilinx FPGAs 5.1.2 Physical Layer tab Figure 14: Physical Layer tab Communication Ports

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-35 5.1.3 Internal Functions tab Figure 15: Internal Functions tab FMMUs Nu

IP Core Configuration III-36 Slave Controller – IP Core for Xilinx FPGAs 5.1.4 Feature Details tab Figure 16: Feature Details tab Base Feature Set

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-37 SyncManager Event Times Distributed Clocks SyncManager Event Times (0x09F0

CONTENTS Slave Controller – IP Core for Xilinx FPGAs III-V 5.1.5 Process Data Interface tab 38 6 Example Designs 45 6.1 Avnet Xilinx Spartan

IP Core Configuration III-38 Slave Controller – IP Core for Xilinx FPGAs 5.1.5 Process Data Interface tab Several interfaces between ESC and the app

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-39 5.1.5.1 No Interface and General Purpose I/O If there is no interface sel

IP Core Configuration III-40 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.2 Digital I/O Configuration The Digital I/O PDI supports up to 4 Byte

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-41 5.1.5.3 µController Configuration (8/16Bit) The 8/16 Bit µController inte

IP Core Configuration III-42 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.4 SPI Configuration The SPI interface is a serial slave interface for

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-43 5.1.5.5 Processor Local Bus (PLB) Configuration The PLB v4.6 PDI connects

IP Core Configuration III-44 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.6 On-Chip Peripheral Bus (OPB) Configuration The OPB PDI connects the

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-45 6 Example Designs Example designs are available for:  Avnet Xilinx Spartan-6

Example Designs III-46 Slave Controller – IP Core for Xilinx FPGAs 6.1 Avnet Xilinx Spartan-6 LX150T Development Kit with Digital I/O 6.1.1 Configu

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-47 6.1.3 Implementation 1. Open Xilinx ISE 2. Open example design <IPInst_dir

CONTENTS III-VI Slave Controller – IP Core for Xilinx FPGAs 9.3 RMII Interface 73 9.3.1 RMII Interface Signals 73 9.3.2 RMII example schematic

Example Designs III-48 Slave Controller – IP Core for Xilinx FPGAs 6.2 Avnet Xilinx Spartan-6 LX150T Development Kit with PLB/AXI 6.2.1 Configurati

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-49 6.2.4 SII EEPROM Use this ESI for the SII EEPROM: Beckhoff Automation GmbH (Eva

FPGA Resource Consumption III-50 Slave Controller – IP Core for Xilinx FPGAs 7 FPGA Resource Consumption The resource consumption figures shown in t

FPGA Resource Consumption Slave Controller – IP Core for Xilinx FPGAs III-51 Table 15: Approximate resource requirements for main configurable func

FPGA Resource Consumption III-52 Slave Controller – IP Core for Xilinx FPGAs The EtherCAT IP core resource consumption figures for typical EtherCAT d

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-53 8 IP Core Signals The available signals depend on the IP Core configuration. 8.

IP Core Signals III-54 Slave Controller – IP Core for Xilinx FPGAs CLK25EtherCAT IP Core Ethernet PHYRMIIREF_CLKDCM/PLLCLK_IN CLK25CLK100CLK100Ethern

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-55 8.3 LED Signals Table 20 lists the signals used for the LEDs. The LED signals a

IP Core Signals III-56 Slave Controller – IP Core for Xilinx FPGAs 8.5 Physical Layer Interface The IP Core is connected with Ethernet PHYs using MI

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-57 8.5.1 MII Interface Table 23 lists the signals used with MII. The TX_CLK signal

CONTENTS Slave Controller – IP Core for Xilinx FPGAs III-VII 10.5.1 Interface 104 10.5.2 Configuration 105 10.5.3 Byte Enable (BE) 105 10.5

IP Core Signals III-58 Slave Controller – IP Core for Xilinx FPGAs Condition Name Direction Description Port2 = MII nMII_LINK2 INPUT 0: 100 Mbit/s

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-59 8.5.2 RMII Interface Table 24 lists the signals used with RMII. Table 24: PHY I

IP Core Signals III-60 Slave Controller – IP Core for Xilinx FPGAs 8.6 PDI Signals 8.6.1 General PDI Signals Table 26 lists the signals available i

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-61 8.6.3 SPI Slave Interface Table 27 used with an SPI PDI. Table 27: SPI PDI Cond

IP Core Signals III-62 Slave Controller – IP Core for Xilinx FPGAs 8.6.4.1 8 Bit µController Interface Table 29 lists the signals used with an 8 Bit

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-63 8.6.5 PLB Processor Local Bus Table 32 lists the signals used with the PLB v4.6

IP Core Signals III-64 Slave Controller – IP Core for Xilinx FPGAs Condi-tion Name Direction Description PDI_PLB_rdPendReq INPUT PLB pending read bus

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-65 8.6.6 OPB On-Chip Peripheral Bus Table 32 lists the signals used with the OPB P

Ethernet Interface III-66 Slave Controller – IP Core for Xilinx FPGAs 9 Ethernet Interface The IP Core is connected with Ethernet PHYs using MII or

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-67 9.1.3 Separate external MII management interfaces If two separate external M

TABLES III-VIII Slave Controller – IP Core for Xilinx FPGAs TABLES Table 1: IP Core Main Features ...

Ethernet Interface III-68 Slave Controller – IP Core for Xilinx FPGAs 9.2 MII Interface The MII interface of the IP Core is optimized for low proces

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-69 9.2.1 MII Interface Signals The MII interface of the IP Core has the followi

Ethernet Interface III-70 Slave Controller – IP Core for Xilinx FPGAs 9.2.2 TX Shift Compensation Since IP Core and the Ethernet PHYs share the same

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-71 Table 36: MII TX Timing characteristics Parameter Comment tCLK25 25 MHz quart

Ethernet Interface III-72 Slave Controller – IP Core for Xilinx FPGAs 9.2.4 MII example schematic Refer to chapter 8.4 for more information on speci

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-73 9.3 RMII Interface The IP Core supports RMII with 2 communication ports. Nev

Ethernet Interface III-74 Slave Controller – IP Core for Xilinx FPGAs 9.3.2 RMII example schematic Refer to chapter 8.4 for more information on spec

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-75 10 PDI Description Table 39: Available PDIs for EtherCAT IP Core PDI number 0x0

PDI Description III-76 Slave Controller – IP Core for Xilinx FPGAs 10.1 Digital I/O Interface 10.1.1 Interface The Digital I/O PDI is selected with

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-77 10.1.2 Configuration The Digital I/O interface is selected with PDI type 0x04 i

TABLES Slave Controller – IP Core for Xilinx FPGAs III-IX Table 61: I²C EEPROM signals ...

PDI Description III-78 Slave Controller – IP Core for Xilinx FPGAs 32Output registerDigital I/O output data register 0x0F00:0x0F03Watchdog&3232EO

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-79 10.1.7 SOF SOF indicates the start of an Ethernet/EtherCAT frame. It is asserte

PDI Description III-80 Slave Controller – IP Core for Xilinx FPGAs SOFDATAInput DATAtSOF_to_DATA_setuptSOFtSOF_to_DATA_hold Figure 36: Digital Input:

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-81 10.2 SPI Slave Interface 10.2.1 Interface An EtherCAT device with PDI type 0x0

PDI Description III-82 Slave Controller – IP Core for Xilinx FPGAs 10.2.3 SPI access Each SPI access is separated into an address phase and a data p

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-83 10.2.5 Commands The command CMD0 in the second address/command byte may be READ

PDI Description III-84 Slave Controller – IP Core for Xilinx FPGAs 10.2.8.1 Read Wait State Between the last address phase byte and the first data b

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-85 10.2.10 2 Byte and 4 Byte SPI Masters Some SPI masters do not allow an arbitrary

PDI Description III-86 Slave Controller – IP Core for Xilinx FPGAs 10.2.11 Timing specifications Table 48: SPI timing characteristics IP Core Paramet

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-87 Table 49: Read/Write timing diagram symbols Symbol Comment A15..A0 Address bits