Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur télécharger pdf (Page 37)

IP Core Installation

Slave Controller – IP Core for Xilinx FPGAs III-25

3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow

3.9 Software Templates for example designs with Microblaze processor (EDK)

Software example templates are available for example designs with Microblaze processor. The

templates have to be copied to your EDK installation folder.

Copy everything inside the templates folder

<IPInst_Dir>\example_designs\SDK_application_templates

to your EDK installation folder

<Xilinx installation folder>\ISE_DS\EDK\sw\lib\sw_apps\

On Windows, the IP Core installation tries to identify EDK installations and integrates the templates

automatically.

For stand-alone SDK installations, copy the templates to your SDK installation folder:

<SDK installation folder>\sw\lib\sw_apps

3.10 EtherCAT Slave Information (ESI) / XML device description for example designs

If you want to use the example designs, add the ESI to your EtherCAT master/EtherCAT configuration

tool/network configurator.

The ESI is located at

<IPInst_dir>\example_designs\EtherCAT_Device_Description\BECKHOFF ET1815.xml

If you are using TwinCAT, add the ESI to the appropriate folder of your TwinCAT installation before

the System Manager is started:

 TwinCAT 2: <TwinCAT installation folder>\Io\EtherCAT

 TwinCAT 3: <TwinCAT installation folder>\<TwinCAT version>\Config\Io\EtherCAT

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur Page 37