Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur télécharger pdf (Page 8)

TABLES

III-VIII Slave Controller – IP Core for Xilinx FPGAs

TABLES

Table 1: IP Core Main Features .............................................................................................................. 1

Table 2: Frame Processing Order ........................................................................................................... 2

Table 3: Tested FPGA/Designflow combinations .................................................................................... 5

Table 4: Release notes ............................................................................................................................ 6

Table 5: Register Revision (0x0001) ....................................................................................................... 7

Table 6: Register Build (0x0002:0x0003) ................................................................................................ 7

Table 7: IP Core Feature Details ........................................................................................................... 11

Table 8: Legend ..................................................................................................................................... 14

Table 9: Register availability.................................................................................................................. 15

Table 10: Legend ................................................................................................................................... 18

Table 11: Extended ESC Features (Reset values of User RAM – 0x0F80:0x0FFF) ............................ 19

Table 12: Contents of lib folder.............................................................................................................. 22

Table 13: Resource consumption Avnet LX150T example design ....................................................... 46

Table 14: Resource consumption Avnet LX150T example design ....................................................... 48

Table 15: Approximate resource requirements for main configurable functions ................................... 51

Table 16: EtherCAT IP Core configuration for typical EtherCAT Devices ............................................ 52

Table 17: EtherCAT IP Core resource consumption for typical EtherCAT Devices .............................. 52

Table 18: General Signals ..................................................................................................................... 53

Table 19: SII EEPROM Signals ............................................................................................................. 54

Table 20: LED Signals ........................................................................................................................... 55

Table 21: DC SYNC/LATCH signals ..................................................................................................... 55

Table 22: Physical Layer General ......................................................................................................... 56

Table 23: PHY Interface MII .................................................................................................................. 57

Table 24: PHY Interface RMII................................................................................................................ 59

Table 25: General PDI Signals .............................................................................................................. 60

Table 26: Digital I/O PDI ........................................................................................................................ 60

Table 27: SPI PDI .................................................................................................................................. 61

Table 28: 8/16 Bit µC PDI ...................................................................................................................... 61

Table 29: 8 Bit µC PDI ........................................................................................................................... 62

Table 30: 16 Bit µC PDI ......................................................................................................................... 62

Table 31: PLB PDI ................................................................................................................................. 63

Table 32: OPB PDI ................................................................................................................................ 65

Table 33: PHY management Interface signals ...................................................................................... 66

Table 34: MII management timing characteristics ................................................................................. 67

Table 35: MII Interface signals .............................................................................................................. 69

Table 36: MII TX Timing characteristics ................................................................................................ 71

Table 37: MII timing characteristics ....................................................................................................... 71

Table 38: RMII Interface signals ............................................................................................................ 73

Table 39: Available PDIs for EtherCAT IP Core .................................................................................... 75

Table 40: IP core digital I/O signals ....................................................................................................... 76

Table 41: Input/Output byte reference ................................................................................................... 76

Table 42: Digital I/O timing characteristics IP Core ............................................................................... 79

Table 43: SPI signals ............................................................................................................................. 81

Table 44: Address modes ...................................................................................................................... 82

Table 45: SPI commands CMD0 and CMD1 ......................................................................................... 83

Table 46: Interrupt request register transmission .................................................................................. 83

Table 47: Write access for 2 and 4 Byte SPI Masters ........................................................................... 85

Table 48: SPI timing characteristics IP Core ......................................................................................... 86

Table 49: Read/Write timing diagram symbols ...................................................................................... 87

Table 50: µController signals ................................................................................................................. 92

Table 51: 8 bit µController interface access types ................................................................................ 93

Table 52: 16 bit µController interface access types .............................................................................. 93

Table 53: µController timing characteristics IP Core ............................................................................. 96

Table 54: PLB signals .......................................................................................................................... 100

Table 55: PLB clock period values for synchronous clocking ............................................................. 101

Table 56: PLB timing characteristics ................................................................................................... 102

Table 57: OPB signals ......................................................................................................................... 104

Table 58: OPB timing characteristics .................................................................................................. 106

Table 59: Distributed Clocks signals ................................................................................................... 108

Table 60: DC SYNC/LATCH timing characteristics IP Core ............................................................... 108

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 125 126

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur Page 8

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