Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur télécharger pdf (Page 108)

PDI Description

III-96 Slave Controller – IP Core for Xilinx FPGAs

10.3.9 Timing Specification

Table 53: µController timing characteristics IP Core

Parameter

Min

Max

Comment

CS_to_BUSY

BUSY driven and valid after CS assertion

ADR_BHE_setup

ADR and BHE valid before RD assertion

RD_to_DATA_driven

0 ns

DATA bus driven after RD assertion

RD_to_BUSY

0 ns

BUSY asserted after RD assertion

read

External read time (RD assertion to BUSY

deassertion) with normal read busy output

(0x0152[0]). Additional 20 ns if delayed read

busy output is configured.

a) t

read_int

a) without preceding write access or

WR_to_RD

≥

prec_write

+ t

Coll

or configuration:

write after falling edge of WR

b) t

read_int

+ t

prec_write

Coll

-t

WR_to_RD

b) with preceding write access and

WR_to_RD

< t

prec_write

+ t

Coll

c) 420 ns

c) 8 bit access, absolute worst case with

preceding write access (t

WR_to_RD

=min

prec_write

=max, t

Coll

=max)

d) 560 ns

d) 16 bit access, absolute worst case with

preceding write access (t

WR_to_RD

=min

prec_write

=max, t

Coll

=max)

read_int

a) 220 ns

b) 300 ns

Internal read time

a) 8 bit access

b) 16 bit access

prec_write

a) 180 ns

b) 260 ns

Time for preceding write access

a) 8 bit access

b) 16 bit access

BUSY_to_DATA_valid

a) x

-5 ns

b) x

-20 ns

DATA bus valid after device BUSY is

deasserted

a) normal read busy output

b) delayed read busy output

ADR_BHE_to_DATA_invalid

0 ns

DATA invalid after ADR or BHE change

CS_RD_to_DATA_release

0 ns

DATA bus released after CS deassertion or

RD deassertion

CS_to_BUSY_release

0 ns

BUSY released after CS deassertion

CS_delay

0 ns

Delay between CS deassertion an assertion

RD_delay

Delay between RD deassertion and

assertion

ADR_BHE_DATA_setup

ADR, BHE and Write DATA valid before WR

deassertion

EtherCAT IP Core: time depends on synthesis results

EtherCAT IP Core: time depends on synthesis results, specified value has to be met anyway

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 125 126

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur Page 108

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