Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur télécharger pdf (Page 53)

IP Core Configuration

Slave Controller – IP Core for Xilinx FPGAs III-41

5.1.5.3 µController Configuration (8/16Bit)

The 8/16 Bit µController interface is an asynchronous parallel interface for µControllers. The difference

between 8 and 16 bit interface is the extended data bus and the BHE signal which enables access to

the upper byte.

Figure 20: Register PDI – µC-Configuration

Busy Configuration

Electrical definition of the busy signal driver

Read BUSY delayed

Delay the output of the BUSY signal by ~20 ns (refer to register 0x00152.0).

Interrupt Configuration

Electrical definition of the interrupt signal driver

Write on falling edge

Start write access earlier with falling edge of nWR. Single write accesses will become slower, but

maximum write access time becomes faster.

Tristate driver for data bus inside core

If Tristate drivers for the data bus should be integrated into the IP Core already activate the check box.

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 125 126

Pas de commentaire

Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur Page 53