Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur télécharger pdf (Page 106)

PDI Description

III-94 Slave Controller – IP Core for Xilinx FPGAs

10.3.6 µController access errors

These reasons for µController access errors are detected by the µController interface:

 Read or Write access to the 16 bit interface with A[0]=1 and BHE(act. low)=1, i.e. an access to an

odd address without Byte High Enable.

 Deassertion of WR (or deassertion of CS while WR remains asserted) while the µController

interface is BUSY.

 Deassertion of RD (or deassertion of CS while RD remains asserted) while the µController

interface is BUSY (read has not finished).

A wrong µController access will have these consequences:

 The PDI error counter 0x030D

will be incremented.

 For A[0]=1 and BHE(act. low)=1 accesses, no access will be performed internally.

 Deassertion of WR (or CS) while the µController interface is BUSY might corrupt the current and

the preceding transfer (if it is not completed internally). Registers might accept write data and

special functions (e.g., SyncManager buffer switching) might be performed.

 If RD (or CS) is deasserted while the µController interface is BUSY (read has not finished), the

access will be terminated internally. Although, internal byte transfers might be completed, so

special functions (e.g., SyncManager buffer switching) might be performed.

The reason of the access error can be read in the PDI error code register 0x030E.

10.3.7 Connection with 16 bit µControllers without byte addressing

If the ESC is connected to 16 bit µControllers/DSPs which only support 16 bit (word) addressing,

ADR[0] and BHE of the EtherCAT device have to be tied to GND, so the ESC will always perform 16

bit accesses. All other signals are connected as usual. Please note that ESC addresses have to be

divided by 2 in this case.

CS CS

ADR[14:0]

BUSY

DATA[15:0]

ADR[15:1]

ADR[0]

BUSY

DATA[15:0]

16 bit µController, async,

only 16 bit addressing

EtherCAT device

IRQ IRQ

BHE

General purpose input EEPROM_Loaded

optional

Figure 47: Connection with 16 bit µControllers without byte addressing

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuel d'utilisateur Page 106