
Features and Registers
III-16 Slave Controller – IP Core for Xilinx FPGAs
V2.4.0-V2.4.4/
V2.04a-V2.04e
Register set
S M L
V2.3.0-V2.3.2/
V2.03a-V2.03d
Register set
S M L
V2.2.1/V2.2.0/
V2.02a
Register set
S M L
DC Sync/Latch
Configuration
Extended PDI
Configuration
Forwarded Rx Error
counter[3:0]
ECAT Processing
Unit Error Counter
Watchdog Time
Process Data
Watchdog Status
Process Data
Watchdog Counter
Process Data
MII Management
Access State
Commentaires sur ces manuels