Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur télécharger pdf (Page 98)

Ethernet Interface

III-86 Slave Controller – IP Core for Xilinx FPGAs

NOTE: A pull-down resistor is typically required for NPHY_RESET_OUT to hold the PHY in reset state while the

FPGA is configured, since this pin is floating or even pulled up during that time.

9.3.2 RMII example schematic

Refer to chapter 8.5.2 for more information on special markings (!). Take care of proper PHY address

configuration.

EtherCAT IP Core

Ethernet PHY

RMII_RX_DV

RMII_RX_DATA[1:0]

RMII_RX_ERR

RMII_TX_ENA

RMII_TX_DATA[1:0]

CRS_DV

RXD[1:0]

RX_ER

TX_EN

TXD[1:0]

REF_CLK

nRMII_LINK LINK_STATUS

CLK25

PLL

CLK_IN CLK25

CLK100

50 MHz

CLK50

NPHY_RESET_OUT

NRESET

4K7

Figure 34: RMII example schematic

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 143 144

Pas de commentaire

Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 98