Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur télécharger pdf (Page 135)

PDI Description

Slave Controller – IP Core for Xilinx FPGAs III-123

10.5.2 Configuration

The AXI4 interface has PDI type 0x80 in the PDI control register 0x0140. The on-chip bus subtype is

“001” for AXI4 and “010” for AXI4LITE in the PDI on-chip bus extended configuration register

0x0152:0x0153. The AXI clock speed, data bus width, and ID width are by generics.

Device emulation

Enable Device emulation (0x0141[0]=1). This feature should be disabled in most use cases, since the

processor will handle the EtherCAT state machine.

On-chip Bus CLK

The AXI bus clock period can be selected from a wide range. Nevertheless, configuring the bus clock

to be a multiple of 25 MHz will result in best performance:

AXI bus clock frequency = N * 25 MHz (N=1...31)

The maximum clock speed depends on the FPGA and the synthesis. The rising edge of AXI clock has

to be synchronous with the rising edge of CLK25 of the EtherCAT IP Core (otherwise the bus clock is

asynchronous).

On-chip Bus CLK is asynchronous to CLK25 core clock

Select this option if the bus clock is asynchronous and synchronization is required (results in extra

delay).

10.5.3 Interrupts

The AXI Slave interface supports up to 3 interrupts for easy connection embedded systems:

 the global PDI interrupt (IRQ_MAIN)

 IRQ_DC_SYNC0 and IRQ_DC_SYNC1. These interrupts are available if DC is selected. The DC

SyncSignals are also available as standard DC Sync0/1 signals.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 135