Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 36
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IP Core Installation
III-24 Slave Controller – IP Core for Xilinx FPGAs
3.2 Installation on Linux PCs
3.2.1 System Requirements
The system requirements of the Xilinx Design tools are applicable. The EtherCAT IP Core
configuration tool has these additional requirements
1
:
Mono 1.2.6 or higher (software for running Microsoft .NET Framework programs, available at
http://www.mono-project.com)
3.2.2 Installation
For installation of the EtherCAT IP Core extract the archive to any folder on your Linux PC (same
contents as on windows PCs):
1. Create installation directory, , e.g. /opt/beckkhoff/ :
# mkdir /opt/beckhoff
2. Change to installation directory
# cd /opt/beckhoff
3. Copy EtherCAT IP Core archive to installation folder
4. Extract the EtherCAT IP Core:
# tar –xf EtherCAT_IP_core_for_Xilinx_FPGAs_<version>_Linux_
<region>.tar.gz
5. Continue with the following installation chapters.
The folder
ethercat_<version>
created inside this directory is further referenced to as <IPInst_dir>.
3.3 Files located in the lib folder
Table 12: Contents of lib folder
File name
Description
EtherCAT_CLK.vhd
Example EtherCAT clock supply
EtherCAT_IPCore.vhd
Encrypted EtherCAT IP Core source code
EtherCAT_Reset.vhd
Example EtherCAT reset supply
pk_ECAT_VENDORID_<company>_Xilinx_RSA.vhd
Vendor ID package (added during
installation, not part of setup)
rsa_ethercat_base_pvt.pem
RSA decryption key for Vendor ID package
rsa_ethercat_ip_<version>_<type>_pvt.pem
RSA decryption key for EtherCAT IP Core
The full version of EtherCAT_IPCore.vhd was
installed.txt
or
The evaluation version of EtherCAT_IPCore.vhd
was installed.txt
Name of this empty text file indicates which
version of EtherCAT_IPCore.vhd is present
in this folder
1
Not all of these variants have been tested with the EtherCAT IP core.
- ® FPGAs 1
- 1 Overview 13
- EtherCAT IP Core 14
- Table 4: Release notes 18
- Figure 3: Design flow 22
- 2 Features and Registers 25
- (0x0108:0x0109) 26
- Table 8: Legend 27
- IP Core 28
- Table 10: Legend 30
- 3 IP Core Installation 35
- 4 IP Core Usage 40
- Figure 7: EDK – Overview 42
- IP Core Usage 44
- 5 IP Core Configuration 46
- Figure 13: Product ID tab 47
- 09) is available if checked 52
- 6 Example Designs 61
- 7 FPGA Resource Consumption 68
- 8 IP Core Signals 71
- CLK25_2NS 72
- Table 19: SII EEPROM Signals 73
- Table 20: LED Signals 73
- PHY Management 75
- Table 23: PHY Interface MII 76
- Table 24: PHY Interface RMII 78
- Table 27: Digital I/O PDI 82
- Table 28: SPI PDI 83
- Table 29: 8/16 Bit µC PDI 83
- Table 30: 8 Bit µC PDI 84
- Table 31: 16 Bit µC PDI 84
- Table 32: PLB PDI 85
- 9 Ethernet Interface 90
- Ethernet PHY 91
- RX_D[3:0] 95
- CLK_IN CLK25 101
- NPHY_RESET_OUT 101
- 10 PDI Description 103
- Digital output pins 106
- LATCH_IN 108
- Figure 43: OUT_ENA timing 109
- Table 47: SPI signals 110
- Table 48: Address modes 111
- SPI_DO (MISO) 116
- SPI_DI (MOSI) 116
- SPI_CLK* 116
- SPI mode 1/3 SPI mode 0/2 117
- PDI Description 118
- 16 bit µController, async 123
- EtherCAT device 123
- 8 bit µController, async 124
- (with preceding write access) 126
- Figure 60: AXI4 signals 133
- Table 61: AXI4 LITE signals 133
- PDI Description 137
- Output event time 138
- EtherCAT 139
- PROM_DATA 139
- PROM_CLK 139
- PROM_SIZE 139
- Table 68: AC Characteristics 140
- Table 69: Forwarding Delays 140
- 14 Synthesis Constraints 141
- 15 Appendix 144
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