Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur télécharger pdf (Page 60)

IP Core Configuration

III-48 Slave Controller – IP Core for Xilinx FPGAs

5.1.5.6 AXI4/AXI4 LITE Configuration

The AXI PDI connects the IP Core with an AXI Master. The data bus width is variable 8/16/32/64 bit.

Figure 23: Register PDI – AXI4/AXI4 LITE Interface Configuration

Device emulation

Enable Device emulation (0x0141[0]=1). This feature should be disabled in most use cases.

On-Chip Bus CLK is asynchronous to CLK25 core clock

Enable if the On-chip BUS CLK is asynchronous to CLK25. Additional synchronization stages are

added in this case.

Interrupt type

Select the usage type of the interrupt signal (level or edge). Since the main interrupt can have different

sources, a level based interrupt is typically required.

Implement Tristate drivers in XPS or export to higher level (XPS configuration option)

This additional option is offered in the “Configure IP” dialog of the EtherCAT IP Core instance inside

EDK. It allows to export the IN/OUT/ENA tristate to higher levels above the XPS, or implement the

tristate driver in the XPS.

Generate pcore for XPS

Enable generation of an EtherCAT IP Core package for Xilinx XPS/EDK, i.e., a pcores folder structure

with source files and module definitions.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 60