Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur télécharger pdf (Page 91)

Ethernet Interface

Slave Controller – IP Core for Xilinx FPGAs III-79

9.1.3 Separate external MII management interfaces

If two separate external MII management interfaces are to be connected to the single MII

management interface of the EtherCAT IP Core, some glue logic has to be added. Disable internal Tri-

State drivers for the MII management bus and combine the signals according to the following figure.

Take care of proper PHY address configuration: the PHYs need different PHY addresses.

EtherCAT IP Core

Ethernet PHY

MDIO_IN

MCLK

MDIO

MDC

4K7

CC I/O

Ethernet PHY

MDIO

MDC

4K7

CC I/O

MDIO_OUT

MDIO_ENA

FPGA

Figure 28: Example schematic with two individual MII management interfaces

9.1.4 MII management timing specifications

For MII Management Interface timing diagrams refer to Section I.

Table 37: MII management timing characteristics

Parameter

Min

Typ

Max

Comment

PRELIMINARY TIMING

MI_startup

1.34 ms

Time between nPHY_RESET_OUT reset end and

the first access via management interface

Clk

400 ns

MI_CLK period

Write

~ 25.6 µs

MI Write access time

Read

~ 25.4 µs

MI Read access time

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 91

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