Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur télécharger pdf (Page 126)

PDI Description

III-114 Slave Controller – IP Core for Xilinx FPGAs

Parameter

Min

Max

Comment

BUSY_to_WR_CS

0 ns

WR or CS deassertion after BUSY

deassertion

WR_to_BUSY

BUSY assertion after WR deassertion

write

0 ns

External write time (WR assertion to BUSY

deassertion)

a) t

write_int

a) Configuration: write after falling edge of

WR (act. low)

b) t

write_int

-t

WR_delay

b) with preceding write access and t

WR_delay

< t

write_int

(Write after rising edge of WR)

c) 0 ns

c) without preceding write access or t

WR_delay

≥ t

write_int

(Write after rising edge of WR)

d) 95 ns

d) 8 bit access, absolute worst case with

preceding write access (t

WR_delay

= min,

WR_int

=max, Write after rising edge of WR)

e) 95 ns

e) 16 bit access, absolute worst case with

preceding write access (t

WR_delay

=min,

WR_int

=max, Write after rising edge of WR)

write_int

a) 55 ns

b) 55 ns

a) 95 ns

b) 95 ns

Internal write time

a) 8 bit access

b) 16 bit access

WR_delay

Delay between WR deassertion and

assertion

WR_to_RD

0 ns

Delay between WR deassertion and RD

assertion

CS_WR_overlap

Time both CS and WR have to be

deasserted simultaneously (only if CS is

deasserted at all)

CS_RD_overlap

Time both CS and RD have to be

deasserted simultaneously (only if CS is

deasserted at all)

CS_RD_to_DATA_release

BHE

ADR_BHE_setup

BHE

DATA

BUSY

DATA

ADR

CS_to_BUSY

read

RD_to_BUSY

RD_delay

CS_delay

BUSY_to_DATA_valid

ADR_BHE_to_DATA_invalid

RD_to_DATA_driven

CS_to_BUSY_release

BHE

ADR

RD_CS_overlap

(with preceding write access)

Internal

state

Reading ADR Idle

read_int

Idle

Figure 53: Read access (without preceding write access)

1 2 ... 121 122 123 124 125 126 127 128 129 130 131 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuel d'utilisateur Page 126

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