Beckhoff EtherCAT Registers Section II Manuel d'utilisateur télécharger pdf (Page 82)

Distributed Clocks (0x0900:0x09FF)

II-70 Slave Controller – Register Description

Table 115: Register Start Time Cyclic Operation (0x0990:0x0993 [0x0990:0x0997])

ESC20

ET1100

ET1200

IP Core

[63:32]

config.

Bit

Description

ECAT

PDI

Reset Value

63:0

Write: Start time (System time) of cyclic

operation in ns

Read: System time of next SYNC0 pulse in

r/(w)

NOTE: Write to this register depends upon setting of 0x0980.0. Only writable if 0x0981.0=0.

Auto-activation (0x0981.3=1): upper 32 bits are automatically extended if only lower 32 bits are written within one

frame.

Table 116: Register Next SYNC1 Pulse (0x0998:0x099B [0x0998:0x099F])

ESC20

ET1100

ET1200

IP Core

[63:32]

config.

Bit

Description

ECAT

PDI

Reset Value

63:0

System time of next SYNC1 pulse in ns

r/-

Table 117: Register SYNC0 Cycle Time (0x09A0:0x09A3)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

31:0

Time between two consecutive SYNC0

pulses in ns.

0: Single shot mode, generate only one

SYNC0 pulse.

r/(w)

NOTE: Write to this register depends upon setting of 0x0980.0.

Table 118: Register SYNC1 Cycle Time (0x09A4:0x09A7)

ESC20

ET1100

ET1200

IP Core

Bit

Description

ECAT

PDI

Reset Value

31:0

Time between SYNC1 pulses and SYNC0

pulse in ns

r/(w)

NOTE: Write to this register depends upon setting of 0x0980.0.

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 97 98

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Beckhoff EtherCAT Registers Section II Manuel d'utilisateur Page 82

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