Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Manuel d'utilisateur Page 33

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Features and Registers
Slave Controller IP Core for Altera FPGAs III-21
Address
Length
(Byte)
Description
IP Core
V3.0.0-
V3.0.10
0x0E08:0x0E0F
8
Vendor ID
x
0x0F00:0x0F03
4
Digital I/O Output Data
io
0x0F10:0x0F17
8
General Purpose Outputs
[Byte]
0-8
0x0F18:0x0F1F
8
General Purpose Inputs [Byte]
0-8
0x0F80:0x0FFF
128
User RAM
x
0x1000:0x1003
4
Digital I/O Input Data
io
0x1000 ff.
Process Data RAM [Kbyte]
1-60
Table 10: Legend
Symbol
Description
x
Available
-
Not available
r
Read only
c
Configurable
dc
Available if Distributed Clocks with all
Sync/Latch signals are enabled
rt
Available if Receive Times or Distributed Clocks
are enabled (always available for 3-4 ports)
io
Available if Digital I/O PDI is selected
red
Register changed in this version
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