Beckhoff CB3056 Manuel d'utilisateur télécharger pdf (Page 60)

Chapter: BIOS Settings Chipset

page 60 Beckhoff New Automation Technology CB3056

4.4.1.1 PCI Express Configuration

Chipset

┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐

│ PCI Express Configuration │Enable or disable PCI Express │

│ │Clock Gating for each root │

│ PCI Express Clock Gating [Enabled] │port. │

│ DMI Link ASPM Control [Enabled] │ │

│ DMI Link Extended Synch Control [Disabled] │ │

│ PCIe-USB Glitch W/A [Disabled] │ │

│ Subtractive Decode [Disabled] │ │

│ │ │

│ PCI Express Root Port 1 │ │

│► PCI Express Root Port 2 │ │

│► PCI Express Root Port 3 │ │

│► PCI Express Root Port 4 │ │

│ PCIE Port 5 is assigned to LAN │────────────────────────────────│

│ PCIE Port 6 is assigned to LAN2 │→←: Select Screen │

│► PCIE Port 7 is assigned to PCIe to PCI Bridge │↑↓: Select Item │

│► PCI Express Root Port 8 │Enter: Select │

│ │+/-: Change Opt. │

│ │F1: General Help │

│ │F2: Previous Values │

│ │F3: Optimized Defaults │

│ │F4: Save & Exit │

│ │ESC: Exit │

│ │ │

└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘

ü PCI Express Clock Gating

Options: Disabled / Enabled

ü DMI Link ASPM Control

Options: Disabled / Enabled

ü DMI Link Extended Synch Control

Options: Disabled / Enabled

ü PCIe-USB Glitch W/A

Options: Disabled / Enabled

ü Subtractive Decode

Options: Disabled

ü PCI Express Root Port X

Sub menu: see "PCI Express Root Port" (p. 61)

Beckhoff CB3056 Manuel d'utilisateur Page 60